vhdl signal mode

2013.02.20 15:12콤퓨타/Hardware

mode : is one of the reserved words to indicate the signal direction.

in : indicates that the signal is an input

out : indicates that the signal is an output of the entity whose valu can only be read by other entities that use it.

buffer: indicates that the signal is an output of the entity whose value can be read inside the entity's architecture

inout : the signal can be an inputor an output

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